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MM74HCT373 * MM74HCT374 3-STATE Octal D-Type Latch * 3-STATE Octal D-Type Flip-Flop
February 1984 Revised May 2005
MM74HCT373 * MM74HCT374 3-STATE Octal D-Type Latch * 3-STATE Octal D-Type Flip-Flop
General Description
The MM74HCT373 octal D-type latches and MM74HCT374 Octal D-type flip flops advanced silicon-gate CMOS technology, which provides the inherent benefits of low power consumption and wide power supply range, but are LS-TTL input and output characteristic & pin-out compatible. The 3-STATE outputs are capable of driving 15 LSTTL loads. All inputs are protected from damage due to static discharge by internal diodes to VCC and ground. When the MM74HCT373 LATCH ENABLE input is HIGH, the Q outputs will follow the D inputs. When the LATCH ENABLE goes LOW, data at the D inputs will be retained at the outputs until LATCH ENABLE returns HIGH again. When a high logic level is applied to the OUTPUT CONTROL input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements. The MM74HCT374 are positive edge triggered flip-flops. Data at the D inputs, meeting the setup and hold time requirements, are transferred to the Q outputs on positive going transitions of the CLOCK (CK) input. When a high logic level is applied to the OUTPUT CONTROL (OC) input, all outputs go to a high impedance state, regardless of what signals are present at the other inputs and the state of the storage elements. MM74HCT devices are intended to interface between TTL and NMOS components and standard CMOS devices. These parts are also plug in replacements for LS-TTL devices and can be used to reduce power consumption in existing designs.
Features
s TTL input characteristic compatible s Typical propagation delay: 20 ns s Low input current: 1 PA maximum s Low quiescent current: 80 PA maximum s Compatible with bus-oriented systems s Output drive capability: 15 LS-TTL loads
Ordering Code:
Order Number MM74HCT373WM MM74HCT373SJ MM74HCT373MTC MM74HCT373N MM74HCT374WM MM74HCT374SJ MM74HCT374MTC MM74HCT374N Package Number M20B M20D MTC20 N20A M20B M20D MTC20 N20A Package Descriptions 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
(c) 2005 Fairchild Semiconductor Corporation
DS005367
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MM74HCT373 * MM74HCT374
Connection Diagrams
Top View MM74HCT373
Top View MM74HCT374
Truth Tables
MM74HCT373 Output Control L L L H H H L X H L X X LE Data 373 Output H L Q0 Z Output Control L L L H MM74HCT374 Clock Data H L X X Output (374) H L Q0 Z
n n
L X
H HIGH Level L LOW Level Q0 Level of output before steady-state input conditions were established. Z High Impedance
H HIGH Level L LOW Level X Don't Care n Transition from LOW-to-HIGH Z High Impedance State The level of the output before steady state input conditions were Q0 established.
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MM74HCT373 * MM74HCT374
Logic Diagrams
MM74HCT373
MM74HCT374
3
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MM74HCT373 * MM74HCT374
Absolute Maximum Ratings(Note 1)
(Note 2) Supply Voltage (VCC) DC Input Voltage (VIN) DC Output Voltage (VOUT) Clamp Diode Current (IIK, IOK) DC Output Current, per pin (IOUT) DC VCC or GND Current, per pin (ICC) Storage Temperature Range (TSTG) Power Dissipation (PD) (Note 3) S.O. Package only Lead Temperature (TL) (Soldering 10 seconds) 260qC 600 mW 500 mW
Recommended Operating Conditions
Min Supply Voltage (VCC) DC Input or Output Voltage (VIN, VOUT) Operating Temperature Range (TA) Input Rise or Fall Times (tr, tf) 500 ns
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Note 2: Unless otherwise specified all voltages are referenced to ground. Note 3: Power Dissipation temperature derating -- plastic "N" package: 12 mW/qC from 65qC to 85qC.
0.5 to 7.0V 1.5 to VCC 1.5V 0.5 to VCC 0.5V r20 mA r35 mA r70 mA 65qC to 150qC
Max 5.5 VCC
Units V V
4.5 0
40
85
qC
DC Electrical Characteristics
VCC 5V r 10% (unless otherwise specified) Parameter Minimum HIGH Level Input Voltage VIL VOH Maximum LOW Level Input Voltage Minimum HIGH Level Output Voltage VIN |IOUT| |IOUT| |IOUT| VOL Maximum LOW Level Voltage VIN |IOUT| |IOUT| |IOUT| IIN IOZ Maximum Input Current Maximum 3-STATE Output Leakage Current ICC Maximum Quiescent Supply Current VIN IOUT VIN VCC or GND 0 PA 2.4V or 0.5V (Note 4) 8.0 1.0 80 1.3 160 1.5 VIN VOUT Enable VIH or VIL 20 PA 6.0 mA, VCC 7.2 mA, VCC VIH or VIL 20 PA 6.0 mA, VCC 7.2 mA, VCC VCC or GND, VCC or GND VIH or VIL 4.5V 5.5V 0 0.2 0.2 0.1 0.26 0.26 0.1 0.33 0.33 0.1 0.4 0.4 V V V 4.5V 5.5V VCC 4.2 5.7 VCC 0.1 3.98 4.98 VCC 0.1 3.84 4.84 VCC 0.1 3.7 4.7 V V V Conditions TA Typ 2.0 0.8 25qC TA Symbol VIH
40 to 85qC
TA
55 to 125qC
Guaranteed Limits 2.0 0.8 2.0 0.8
Units V V
VIH or VIL
r0.1
r1.0
r1.0
PA
r0.5
r5.0
r10
PA
PA
mA
Note 4: Measured per pin. All others tied to VCC or ground.
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4
MM74HCT373 * MM74HCT374
AC Electrical Characteristics
MM74HCT373: VCC Symbol tPHL, tPLH tPHL, tPLH tPZH, tPZL tPHZ, tPLZ tW tS tH
5.0V, tr
tf
6 ns TA 25qC (unless otherwise specified)
Conditions CL CL CL RL CL RL 45 pF 45 pF 45 pF 1 k: 5 pF 1 k: Typ 18 21 20 18 Guaranteed Limit 25 30 28 25 16 5 10 Units ns ns ns ns ns ns ns
Parameter Maximum Propagation Delay Data to Output Maximum Propagation Delay Latch Enable to Output Maximum Enable Propagation Delay Control to Output Maximum Disable Propagation Delay Control to Output Minimum Clock Pulse Width Minimum Setup Time Data to Clock Minimum Hold Time Clock to Data
AC Electrical Characteristics
MM74HCT373: VCC Symbol
5.0V r 10%, tr
Parameter
tf 6 ns (unless otherwise specified)
Conditions CL CL CL CL CL CL RL CL RL CL 50 pF 150 pF 50 pF 150 pF 50 pF 150 pF 1 k: 50 pF 1 k: 50 pF 8 12 16 5 10 10 20 OC OC VCC GND 5 52
CPD VCC2 f ICC VCC, and the no load dynamic current consumption,
TA 25qC Typ 22 30 25 32 21 30 21 30 40 35 45 30 40 30
TA 40 to 85qC TA 55 to 125qC Guaranteed Limits 37 50 44 56 37 50 37 15 20 6 13 10 20 45 60 53 68 45 60 45 18 24 8 20 10 20
Units ns ns ns ns ns ns ns ns ns ns ns pF pF pF pF
tPHL, tPLH Maximum Propagation Delay Data to Output tPHL, tPLH Maximum Propagation Delay Latch Enable to Output tPZH, tPZL Maximum Enable Propagation Delay Control to Output tPHZ, tPLZ Maximum Disable Propagation Delay Control to Output tTHL, tTLH Maximum Output Rise and Fall Time tW tS tH CIN COUT CPD Minimum Clock Pulse Width Minimum Setup Time Data to Clock Minimum Hold Time Clock to Data Maximum Input Capacitance Maximum Output Capacitance Power Dissipation Capacitance (Note 5)
Note 5: CPD determines the no load dynamic power consumption, PD IS CPD VCC f ICC.
5
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MM74HCT373 * MM74HCT374
AC Electrical Characteristics
MM74HCT374: VCC Symbol fMAX tPHL, tPLH tPZH, tPZL tPHZ, tPLZ tW tS tH
5.0V, tr
tf
6 ns TA 25qC (unless otherwise specified)
Conditions Typ 50 CL CL RL CL RL 45 pF 45 pF 1 k: 5 pF 1 k: 20 5 16 ns ns ns 17 25 ns 20 19 Guaranteed Limit 30 32 28 Units MHz ns ns
Parameter Maximum Clock Frequency Maximum Propagation Delay to Output Maximum Enable Propagation Delay Control to Output Maximum Disable Propagation Delay Control to Output Minimum Clock Pulse Width Minimum Setup Time Data to Clock Minimum Hold Time Clock to Data
AC Electrical Characteristics
MM74HCT374: VCC Symbol fMAX
5.0V r 10%, tr
Parameter
tf 6 ns (unless otherwise specified)
Conditions TA Typ 30 CL CL CL CL RL CL RL CL 50 pF 150 pF 50 pF 150 pF 1 k: 50 pF 1 k: 50 pF 8 12 16 20 5 10 20 OC OC VCC GND 5 58
CPD V CC2 f ICC VCC, and the no load dynamic current consumption, IS
25qC
TA
40 to 85qC TA 55 to 125qC
Guaranteed Limits 24 45 57 37 50 37 15 20 25 5 10 20 20 48 69 45 60 45 18 24 30 5 10 20
Units MHz ns ns ns ns ns ns ns ns ns pF pF pF pF
Maximum Clock Frequency 22 30 21 30 21 to Output
tPHL, tPLH Maximum Propagation Delay tPZH, tPZL Maximum Enable Propagation Delay Control to Output tPHZ, tPLZ Maximum Disable Propagation Delay Control to Output tTHL, tTLH Maximum Output Rise and Fall Time tW tS tH CIN COUT CPD Minimum Clock Pulse Width Minimum Setup Time Data to Clock Minimum Hold Time Clock to Data Maximum Input Capacitance Maximum Output Capacitance Power Dissipation Capacitance (Note 6)
36 46 30 40 30
Note 6: CPD determines the no load power consumption, PD
CPD VCC f I CC.
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6
MM74HCT373 * MM74HCT374
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B
7
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MM74HCT373 * MM74HCT374
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D
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MM74HCT373 * MM74HCT374
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC20
9
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MM74HCT373 * MM74HCT374 3-STATE Octal D-Type Latch * 3-STATE Octal D-Type Flip-Flop
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 10 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

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